For this type of a signal line driver, a bus driver, a line driver, etc. can be used.
FIG. 6 shows a circuit diagram for a conventional address driver that is used in an address buffer or the like within a semiconductor memory device. FIG. 7 shows the signal waveform of each section of this address driver.
This address driver is designed with a one bit address signal input (AIN), and a pair of complementary address signal outputs (AOUT, AOUT_) having either an H level or an L level in response to the logic value of this input address signal (AIN).
This address driver is constructed of input stage inverters 100, 102, 104 that regulate the voltage level of the input address signal (AIN) to the logic level of a reference voltage, NAND gates 106, 108 that regulate the pulse period of the output address signals (AOUT, AOUT_), and the output stage inverters 110, 112 that electrically drive the pair of bus lines (AL, AL_), respectively, in order to transmit the output address signals (AOUT, AOUT_). The other end (receive end) of the bus lines (AL, AL_) are connected at the receiver side, for example, to the input terminal of an input buffer for an address decoder or a receiver (not illustrated).
In the interval that the address signals (AOUT, AOUT_) are not output, the address enable signal (AEN) is in an inactive state (L level), the outputs of both NAND gates 106, 108 are each held at an H level, and the outputs of both inverters 110, 112 and the bus lines (AL, AL) are all held at an L level that is equal to the power supply voltage (V.sub.SS) (for example, 0 volts).
At the same time an address signal (AIN) is input, an address enable signal (AEN) is activated for a prescribed period, for example, for the pulse period, and during this pulse period, both NAND gates 106, 108 are turned on.
When the logic level of the address signal (AIN) is "1" (H level), the output of the NAND gate 106 becomes an L level, and due to this, the output of the inverter 110 becomes an H level that is nearly equal to the power supply voltage (V.sub.DD) (for example, 3.3 volts). On the other hand, the output of the NAND gate 108 remains at the H level, and the output of the inverter 112 remains at the L level that is equal to (V.sub.SS). By this means, during the pulse period that is regulated by means of the address enable signal (AEN), an address signal (AOUT) having an H level that is nearly equal to (V.sub.DD) is output on the bus line (AL); and a complementary address signal AOUT_) having an L level that is nearly equal to (V.sub.SS) is output on the bus line AL_.
Conversely, when the logic value of the address signal (AIN) is "0" (L level), during the pulse period, an address signal (AOUT) having an L level that is nearly equal to (V.sub.SS) is output on one of the bus lines (AL), and a complementary address signal (AOUT_) having an H level that is nearly equal to (V.sub.DD) is output on the other bus line (AL_).
Problems to be solved by the invention
As was mentioned above, a conventional signal line driver of this type can transmit and output a binary signal having an H level that is nearly equal to (V.sub.DD) and an L level that is nearly equal to (V.sub.SS) due to the fact that the output stage inverters 110, 112 drive the signal lines (bus lines) AL, AL_at the full amplitude of both power supply voltages (V.sub.DD, V.sub.SS).
However, in a DRAM (dynamic RAM), for example, as the storage capacity increases, the chip surface area also increases and the signal lines within the chip become longer, and the transmission delay time on the bus becomes impossible to ignore. Also, in a high-speed memory such as a synchronous DRAM, the transfer cycle for the signal is fast, and because as a general rule the address width (number of address bits) is also large, the electrical power that is consumed by the bus driver also becomes impossible to ignore.
The present invention was designed with consideration of these types of problems, and its purpose is to disclose a signal line driver that reduces the power consumption and shortens the transmission delay time.